1. Field of the Invention
The present invention generally relates to a wiring substrate and a method of manufacturing the wiring substrate. For example, there is a wiring substrate including a substrate body formed having a penetration electrode and a pad to which the penetration electrode and an electronic component are electrically connected, and a method for manufacturing the wiring substrate.
2. Description of the Related Art
FIG. 1 is a cross-sectional diagram illustrating a semiconductor device 200 according to a related art example. In FIG. 1, the semiconductor device 200 includes a wiring substrate 201, electronic components 202, 203, and external connection terminals 205, 206.
The wiring substrate 201 includes a substrate body 211, an insulating film 212, penetration electrodes 213, 214, wiring patterns 216-218, 221, 222, and solder resist layers 225, 226.
Further, through holes 231, 232 are formed in the substrate body 211. The substrate body 211 may be, for example, a silicon substrate, a compound (e.g., GaAs) semiconductor substrate, or a glass substrate (including a quartz glass substrate).
The insulating film 212 is formed in a manner covering an upper surface 211A and a lower surface 211E of the substrate body 211, and the surfaces of the substrate body 211 face the side surfaces of the through holes 231, 232.
The penetration electrode 213 is provided in the through hole 231 which has the insulating film 212 formed therein. The penetration electrode 214 is provided in the through hole 232 which has the insulating film 212 formed therein.
The wiring pattern 216 is provided on the insulating film 212 formed on the upper surface 211A of the substrate body 211. The wiring pattern 216 is connected to an upper end of the penetration electrode 213. The wiring pattern 216 includes a pad 216A on which the electronic component 203 is mounted.
The wiring pattern 217 is provided on the insulating film 212 formed on the upper surface 211A of the substrate body 211. The wiring substrate 217 is connected to an upper end of the penetration electrode 214. The wiring pattern 217 includes a pad 217A on which the electronic component 202 is mounted.
The wiring pattern 218 is provided on the insulating film 212 located between the electronic components 202 and 203. One end part of the wiring pattern 218 is connected to the pad 216A. The other end part of the wiring part 218 is connected to the pad 217A.
The wiring pattern 221 is provided on a lower surface of the insulating film 212 formed on the lower surface 211B of the substrate body 211. The wiring pattern 221 is connected to a lower end of the penetration electrode 213. Thereby, the wiring pattern 221 is electrically connected to the wiring pattern 216 via the penetration electrode 213. The wiring pattern 221 includes an external connection pad 221A.
The wiring pattern 222 is provided on a lower surface of the insulating film 212 formed on the lower surface 211B of the substrate body 211. The wiring pattern 222 is connected to a lower end of the penetration electrode 214. Thereby, the wiring pattern 222 is electrically connected to the wiring pattern 217 via the penetration electrode 214. The wiring pattern 222 includes an external connection pad 222A.
The solder resist layer 225 is formed on the insulating film 212 in a manner covering the wiring patterns 216-218 except for the areas where the pads 216A, 217A are formed. The solder resist layer 225 includes an opening part 225A exposing the pad 216A and an opening part 225B exposing the pad 217A.
The solder resist layer 226 is formed on the lower surface of the insulating film 212 in a manner covering the wiring patterns 221 and 222 except for the areas where the pads 221A, 222A are formed. The solder resist layer 226 includes an opening part 226A exposing the pad 221A and an opening part 226B exposing the pad 222A.
The electronic component 202 is connected to the pad 217A by flip-chip bonding. The electronic component 203 is connected to the pad 216A by flip-chip bonding. The electronic component 203 is electrically connected to the electronic component 202 via the wiring pattern 218.
The external connection terminal 205 is formed on the pad 221A. The external connection terminal 206 is formed on the pad 222A. The external connection terminals 205, 206 serve as terminals (e.g., solder balls) that are to be electrically connected to pads (not illustrated) of a target mounting substrate (not illustrated) when the semiconductor device 200 is mounted on the target mounting substrate (See, for example, Japanese Laid-Open Patent Application No. 2006-135174).
FIG. 2 is a schematic diagram for describing problems of a wiring substrate according to a related art example. In FIG. 2, like components are denoted with like reference numerals of the semiconductor device 200 of FIG. 1.
In a case where a substrate such as a silicon substrate, a compound (e.g., GaAs) semiconductor substrate, or a glass substrate (including a quartz glass substrate) is used as the substrate body 211, the substrate body 211 is more fragile compared to a resin substrate.
The outer peripheral part (including corner parts of the substrate body 211) of the substrate body 211 may be broken during handling (for example, the handling from completing the fabrication of the wiring substrate 11 to mounting the electronic components 12, 13 on the wiring substrate 11) of the wiring substrate 201. As a result, a chipped part(s) 250 may be formed in the substrate body 211 as illustrated in FIG. 2.